Technical Field
The present invention relates to techniques for testing semiconductor chips. More specifically, the present invention relates to methods and apparatuses for generating test patterns for detecting faults in semiconductor chips.
Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including hundreds of millions of transistors, onto a single semiconductor chip. This dramatic increase in semiconductor integration densities has made it considerably more challenging to efficiently test semiconductor devices after device manufacturing. Defects (systematic and random) introduced during manufacturing process may cause a signal line to get broken or shorted with another line resulting in the manufactured chip to fail. Moreover, a semiconductor chip may meet timing constraints during the design phase, however, a manufactured semiconductor chip may contain defects, due to process variations and other factors, which may result in a delay violation causing the chip to fail. These defects can be modeled as faults (such as stuck-at, transition, path-delay, bridging, etc.) and be detected by generating appropriate test patterns.
Automatic test pattern generation (ATPG) techniques obtain their efficiency by covering a large set of easy-to-detect faults first, and then targeting individual hard-to-detect faults. Usually, a pattern generated to detect a single fault ends up fortuitously detecting many other faults. Test pattern generation algorithms leverage this notion of fortuitous detection by performing fault simulation on every pattern generated to eliminate the faults fortuitously detected by the given pattern from the fault list.
Conventional automatic test pattern generation (ATPG) engines/techniques typically assume all faults are equally likely to occur and therefore assign equal weight to each fault during test pattern generation. Consequently, every single fault is equally important from testing point of view. Note that it is impractical to cover all possible faults on millions of sites within a reasonable amount of time. As a result, faults that are harder to test are not sufficiently covered by the conventional techniques. Note that such techniques have been fairly effective when the escape rate, or the defective parts per million (DPPM) level is high. However, as acceptable DPPM levels continue to decrease and IC manufacturers aggressively pursue an objective of near zero DPPM, the conventional ATPG techniques have become increasingly ineffective.
Another potential problem associated with conventional ATPG techniques lies in the fact that high fault coverage usually does not guarantee high defect coverage. This is because when an ATPG technique assumes all faults are equally likely to occur, the easy-to-occur but hard-to-detect faults (i.e., the high risk faults) become less likely to be detected than the easy-to-detect faults. As a result, the high risk faults are often not treated effectively with the current techniques. For example, when an ATPG technique achieves 98% fault coverage, the remaining 2% of the uncovered faults can represent significantly more than 2% of the risk of defects.
Hence, what is needed is a method and an apparatus for generating test patterns for more effective fault coverage in detecting defects in semiconductor chips without the problems described above.